The present invention relates to a digital reproduction signal processor, and more particularly, to a digital reproduction signal processor which is employed in a reproduction apparatus for a digital recording medium such as an optical disc and a magnetic disk.
In recent years, in information recording media such as an optical disk and a magnetic disk, technological developments for aiming increases in the capacity and in the transfer speed have been prompted. Especially, improvements in basic performances of an information recording medium and a reading head for reading out information from the information recording medium are raised. In addition, improvements in reading accuracy and techniques such as higher multiple speed operation, which refers to the digital reproduction signal processor are raised.
The digital reproduction signal processor relates to a technique for taking out, from signals which are read from a recording medium by the reading head, an accurate recorded data, even from a signal in a bad state due to superposition of noises and inter-codes interferences, employing a high digital signal processing technique.
Further, in a field of a magnetic disk in-which researches in digital reproduction signal processors have been most advancing, an analog reproduction signal processing method called as xe2x80x9ca peak detectionxe2x80x9d is mainly employed. This method is a technique, in which differentiation is analogously performed to a reproduction signal, thereby detecting a peak pattern of a signal and taking out a recorded data. The above-described technique provides effects that quite a simple circuit can be structured, and further, that it can realize a high speed apparatus that is operated with low power consumption.
However, according to a recent digital reproduction signal processor, most of reproduction signal processing methods for a magnetic disk have been shifted from the above-described analog detecting method called as xe2x80x9ca peak detectionxe2x80x9d to a digital reproduction signal processing technique called as xe2x80x9cPRML (Partial Response Maximum Likelihood) methodxe2x80x9d.
This PRML method is a digital reproduction signal processing method which is obtained by combining a partial response method as a technique of a communication system and a maximum likelihood as a code theory. This PRML method shows superior characteristics in reproduction ability of high-density recorded signals, with relative to an analog reproduction signal processor. Therefore, in the field of the magnetic disk, most of the analog reproduction signal processors have been replaced by the PRML method.
Further, in recent years, digital reproduction signal processing such as the PRML method has been examined also in a field of an optical disk, similarly as in the magnetic disk.
A conventional digital reproduction signal processor will be hereinafter described.
FIG. 13 is a block diagram illustrating a structure of a conventional digital reproduction signal processor employing a PRML method.
Initially, an analog signal read from a recording medium 101 by a reading head 102 is input to an analog filter 103. As for the analog reproduction signal input into the analog filter 103, high frequency noises thereof are cut off by the analog filter 103, and signal components of a specific band are emphasized. Next, the analog reproduction signal, which was filtered by the analog filter 103, is input into an analog/digital converter 104. The analog/digital converter 104 converts the analog reproduction signal to a digital reproduction signal at a timing, which is synchronized to a channel rate of the analog signal. The digital reproduction signal output from the analog/digital converter 104 is input into an FIR filter 105. The FIR filter is a digital filter for equalizing the digital reproduction signal.
Further, an output of the FIR filter 105 is input to a coefficient setting unit 106 and a Viterbi decoder 107. At this timing, in the coefficient setting unit 106, an optimized equivalent coefficient of the FIR filter is calculated from output data of the FIR filter 105 with employing an algorithm of Least Mean Square (hereinafter, referred to as LMS), thereby performing an equivalent coefficient setting. Further, the Viterbi decoder 107 performs the maximum likelihood according to output data stream output from the FIR filter 105, thereby to output a binary signal.
As described above, when the PRML method is employed, the reproduction signal processor can perform a reproduction without extremely intensifying high frequency noises. Further, even in a data pattern which is judged to be an error by a level judgement, the Viterbi decoder 107 can perform corrections, thereby reading more accurately a recorded reproduction signal.
However, the conventional digital reproduction signal processor has a problem in sharply increasing a circuit size and power consumption as compared with the conventional analog reproduction signal processor.
As described in the above-described prior art, according to the digital reproduction signal processor, most of the circuits are realized by digital circuits. Therefore, the digital reproduction signal processor requires an analog/digital converter which operates at a high speed and a digital circuit which operates at a high speed. More particularly, the analog/digital converter and the digital circuit are required to operate at a channel rate, which is a standard unit for writing digital data. The channel rate has the highest frequency among the drive systems. When the digital reproduction signal processor is operated at such a high frequency, the power consumption of the analog/digital converter is increased, and power consumption of logic circuits which are operated at high speeds are also increased in the same manner.
Further, in recent years, speed-up in a hard disk apparatus and an optical disk apparatus have been rapidly advanced. Especially, the reproduction speed of CD-ROM which is an optical disc oriented for only reading has been tremendously advancing from one multiple speed reproduction at the beginning of the development, to a forty multiple speed reproduction drive in recent days. Also, for a DVD-ROM, before it is fully diffused, a competition in realizing a higher multiple speed has already started.
However, when a higher multiple speed has progressed more and more, the channel rate will have a higher frequency, and when the frequency becomes higher, it results in a problem that realizing an efficient digital reproduction signal processing becomes difficult.
Initially, when the channel rate has become a high frequency, it is difficult to realize an analog/digital converter operating at a high speed. Even when it has become possible to operate an analog/digital converter at a high speed, the power consumption becomes extremely large. Also, for the digital circuit, as the channel rate becomes higher, it becomes more and more difficult to realize a high speed digital circuit. Further, even though the high speed digital circuit can be realized, the realization thereof might cause a problem that the cost as well as the power consumption should increase.
Further, as for the drives such as an HDD and a DVD-ROM, an increased power consumption cannot be accepted, even if a multiple speed performance is improved. Further, a digital signal processor installed in a note type personal computer is required to operate with a further lowered power consumption.
As described above, while the performance is progressed and the reading accuracy is improved in the conventional digital reproduction signal processor, it is difficult to realize speeding up of operation because of an increased power consumption.
The present invention is made to solve the above-described problems and it has for its object to provide a digital reproduction signal processor operating with low power consumption and of low cost by reducing an analog/digital converter or a digital circuit operating at a channel rate, even when a digital reading channel employing the PRML can be realized.
In order to realize the above-described objects, according to the present invention (claim 1), there is provided a digital reproduction signal processor which judges a digital recorded data from an analog reproduction signal which is read from a recording medium by a reading head, the digital reproduction signal processor, comprising: at least an analog/digital converter for sampling the analog digital reproduction signal at a period which is longer than the digital recording channel rate, and converting the same to a low rate digital reproduction signal having a period which is longer than that of the digital recording channel rate; an equalizing circuit for performing a digital filtering to the low rate digital reproduction signal with keeping the low rate, to generate a digital equalization signal; an interpolator for interpolating reproduction data with the digital recording channel rate from the digital equalization signal; a judging unit for the judging recorded data from the data stream interpolated by the interpolator.
According to the digital reproduction signal processor as constructed above, an analog/digital converter or digital circuits operated at a channel rate can be eliminated, thereby realizing an apparatus operating with low power consumption and of low cost.
According to the present invention (claim 2), there is provided a digital reproduction signal processor of claim 1, wherein the digital/analog converter performs a sampling at a half rate which is a half frequency of the recording channel rate.
According to the digital reproduction signal processor as constructed above, even employing a low frequency rate, it is possible to exhibit performances equivalent to those obtained by a channel rate processing.
According to the present invention (claim 3), there is provided a digital reproduction signal processor of claim 1, wherein the interpolator performs a Nyquist interpolation the band of which is limited to a half-rate Nyquist frequency.
According to the digital reproduction signal processor as constructed above, unwanted emphasis of high frequency components can be prevented, thereby providing improved interpolation characteristics.
According to the present invention (claim 4), there is provided a digital reproduction signal processor of claim 1, wherein the interpolation performs a partial response interpolation which corresponds to the partial response transmission characteristics.
According to the digital reproduction signal processor as constructed above, it is possible to obtain efficient interpolation characteristics having no unwanted noise emphasis.
According to the present invention (claim 5), there is provided a digital reproduction signal processor of claim 1, wherein the judging unit is constituted by a Viterbi decoder which can perform a half-rate operation.
According to the digital reproduction signal processor as constructed above, it is possible to simultaneously calculate existing probabilities of plural branches.
According to the present invention (claim 6), the digital reproduction signal processor of claim 1, wherein the judging unit performs an operation with one or more a code length constraint in modulation code.
According to the digital reproduction signal processor as constructed above, it is possible to reduce paths of the Viterbi decoder with employing the one or more of code length constraint in modulation code.